mirror of https://github.com/llvm/torch-mlir
Add sigmoid lowering
Follows existing conventions for activation functionspull/296/head
parent
29e1b2fe89
commit
d9df4bfc95
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@ -149,7 +149,6 @@ class ElementwiseFlattenBroadcastModule(torch.nn.Module):
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def ElementwiseFlattenBroadcastModule_basic(module, tu: TestUtils):
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def ElementwiseFlattenBroadcastModule_basic(module, tu: TestUtils):
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module.forward(tu.rand(6), tu.rand())
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module.forward(tu.rand(6), tu.rand())
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# ==============================================================================
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# ==============================================================================
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@ -169,3 +168,24 @@ class ElementwiseReluModule(torch.nn.Module):
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@register_test_case(module_factory=lambda: ElementwiseReluModule())
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@register_test_case(module_factory=lambda: ElementwiseReluModule())
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def ElementwiseReluModule_basic(module, tu: TestUtils):
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def ElementwiseReluModule_basic(module, tu: TestUtils):
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module.forward(tu.rand(4, 2) - 0.5)
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module.forward(tu.rand(4, 2) - 0.5)
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# ==============================================================================
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class ElementwiseSigmoidModule(torch.nn.Module):
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def __init__(self):
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super().__init__()
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@export
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@annotate_args([
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None,
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([-1, -1], torch.float32, True),
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])
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def forward(self, x):
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return torch.sigmoid(x)
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@register_test_case(module_factory=lambda: ElementwiseSigmoidModule())
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def ElementwiseSigmoidModule_basic(module, tu: TestUtils):
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module.forward(tu.rand(3, 5))
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@ -436,6 +436,7 @@ def emit_aten_ops(torch_ir_dir: str, registry: Registry):
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for key in [
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for key in [
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"aten::tanh : (Tensor) -> (Tensor)",
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"aten::tanh : (Tensor) -> (Tensor)",
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"aten::relu : (Tensor) -> (Tensor)",
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"aten::relu : (Tensor) -> (Tensor)",
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"aten::sigmoid : (Tensor) -> (Tensor)",
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"aten::sin : (Tensor) -> (Tensor)",
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"aten::sin : (Tensor) -> (Tensor)",
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"aten::exp : (Tensor) -> (Tensor)",
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"aten::exp : (Tensor) -> (Tensor)",
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"aten::cos : (Tensor) -> (Tensor)",
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"aten::cos : (Tensor) -> (Tensor)",
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@ -71,6 +71,34 @@ def Torch_AtenRelu_Op : Torch_Op<"aten.relu_", [
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let assemblyFormat = "$self attr-dict `:` type($self) `->` type($result)";
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let assemblyFormat = "$self attr-dict `:` type($self) `->` type($result)";
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}
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}
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def Torch_AtenSigmoidOp : Torch_Op<"aten.sigmoid", [
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AllowsTypeRefinement,
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HasValueSemantics
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]> {
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let summary = "Generated op for `aten::sigmoid : (Tensor) -> (Tensor)`";
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let arguments = (ins
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AnyTorchTensorType:$self
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);
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let results = (outs
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AnyTorchTensorType:$result
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);
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let assemblyFormat = "$self attr-dict `:` type($self) `->` type($result)";
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}
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def Torch_AtenSigmoid_Op : Torch_Op<"aten.sigmoid_", [
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IsTrailingUnderscoreInplaceVariant,
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AllowsTypeRefinement
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]> {
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let summary = "Generated op for `aten::sigmoid_ : (Tensor) -> (Tensor)`";
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let arguments = (ins
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AnyTorchTensorType:$self
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);
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let results = (outs
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AnyTorchTensorType:$result
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);
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let assemblyFormat = "$self attr-dict `:` type($self) `->` type($result)";
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}
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def Torch_AtenSinOp : Torch_Op<"aten.sin", [
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def Torch_AtenSinOp : Torch_Op<"aten.sin", [
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AllowsTypeRefinement,
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AllowsTypeRefinement,
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HasValueSemantics
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HasValueSemantics
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@ -654,6 +654,14 @@ static Value createLinalgPayloadCalculationForElementwiseOp(
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ArrayRef<Value> operands) {
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ArrayRef<Value> operands) {
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if (isa<AtenTanhOp>(op))
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if (isa<AtenTanhOp>(op))
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return b.create<math::TanhOp>(loc, payloadArgs[0]);
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return b.create<math::TanhOp>(loc, payloadArgs[0]);
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if (isa<AtenSigmoidOp>(op)){
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Type elementType = payloadArgs[0].getType();
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auto one = b.create<ConstantOp>(loc, FloatAttr::get(elementType, 1));
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auto negate = b.create<NegFOp>(loc, payloadArgs[0]);
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auto exp = b.create<math::ExpOp>(loc, negate);
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auto added = b.create<AddFOp>(loc, exp, one);
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return b.create<DivFOp>(loc, one, added);
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}
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if (auto relu = dyn_cast<AtenReluOp>(op)) {
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if (auto relu = dyn_cast<AtenReluOp>(op)) {
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if (!relu.getType()
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if (!relu.getType()
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.cast<ValueTensorType>()
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.cast<ValueTensorType>()
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@ -775,7 +783,8 @@ struct ConvertElementwiseOp : ConversionPattern {
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matchAndRewrite(Operation *op, ArrayRef<Value> operands,
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matchAndRewrite(Operation *op, ArrayRef<Value> operands,
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ConversionPatternRewriter &rewriter) const override {
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ConversionPatternRewriter &rewriter) const override {
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if (!isa<AtenTanhOp, AtenReluOp, AtenAddTensorOp, AtenMulTensorOp,
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if (!isa<AtenTanhOp, AtenReluOp, AtenAddTensorOp, AtenMulTensorOp,
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AtenDivTensorOp, AtenSubTensorOp, AtenLerpTensorOp>(op))
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AtenDivTensorOp, AtenSubTensorOp, AtenLerpTensorOp,
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AtenSigmoidOp>(op))
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return rewriter.notifyMatchFailure(op, "not a supported elementwise op");
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return rewriter.notifyMatchFailure(op, "not a supported elementwise op");
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if (failed(verifyLinalgCompatibleTypes(op, rewriter)))
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if (failed(verifyLinalgCompatibleTypes(op, rewriter)))
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@ -1137,7 +1146,8 @@ public:
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patterns.add<ConvertAtenBatchNormOp>(typeConverter, context);
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patterns.add<ConvertAtenBatchNormOp>(typeConverter, context);
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target
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target
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.addIllegalOp<AtenTanhOp, AtenReluOp, AtenAddTensorOp, AtenMulTensorOp,
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.addIllegalOp<AtenTanhOp, AtenReluOp, AtenAddTensorOp, AtenMulTensorOp,
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AtenDivTensorOp, AtenSubTensorOp, AtenLerpTensorOp>();
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AtenDivTensorOp, AtenSubTensorOp, AtenLerpTensorOp,
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AtenSigmoidOp>();
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patterns.add<ConvertElementwiseOp>(typeConverter, context);
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patterns.add<ConvertElementwiseOp>(typeConverter, context);
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target.addIllegalOp<AtenUnsqueezeOp>();
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target.addIllegalOp<AtenUnsqueezeOp>();
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patterns.add<ConvertAtenUnsqueezeOp>(typeConverter, context);
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patterns.add<ConvertAtenUnsqueezeOp>(typeConverter, context);
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@ -175,7 +175,7 @@ public:
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AtenSubScalarOp, AtenMulScalarOp, AtenDivScalarOp, AtenFmodScalarOp,
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AtenSubScalarOp, AtenMulScalarOp, AtenDivScalarOp, AtenFmodScalarOp,
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AtenFloorDivideScalarOp, AtenEqScalarOp, AtenGeScalarOp,
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AtenFloorDivideScalarOp, AtenEqScalarOp, AtenGeScalarOp,
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AtenNeScalarOp, AtenBitwiseNotOp, AtenToDtypeOp, AtenExpOp,
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AtenNeScalarOp, AtenBitwiseNotOp, AtenToDtypeOp, AtenExpOp,
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AtenSinOp, AtenCosOp, DerefineOp>(op)) {
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AtenSinOp, AtenCosOp, AtenSigmoidOp, DerefineOp>(op)) {
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return getLatticeElement(op->getResult(0)).join(*operands[0]);
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return getLatticeElement(op->getResult(0)).join(*operands[0]);
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}
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}
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