mirror of https://github.com/llvm/torch-mlir
parent
17c3c15131
commit
e60160d793
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@ -1201,21 +1201,6 @@ class DecomposeAtenIsposinfOp : public OpRewritePattern<AtenIsposinfOp> {
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};
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} // namespace
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namespace {
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class DecomposeAtenNonzeroOp : public OpRewritePattern<AtenNonzeroOp> {
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public:
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using OpRewritePattern<AtenNonzeroOp>::OpRewritePattern;
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LogicalResult matchAndRewrite(AtenNonzeroOp op,
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PatternRewriter &rewriter) const override {
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Location loc = op.getLoc();
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Value zeroScalar =
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rewriter.create<ConstantIntOp>(loc, rewriter.getI64IntegerAttr(0));
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rewriter.replaceOpWithNewOp<AtenNeScalarOp>(op, op.getType(), op.getSelf(),
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zeroScalar);
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return success();
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}
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};
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} // namespace
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namespace {
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class DecomposeAtenReshapeOp : public OpRewritePattern<AtenReshapeOp> {
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public:
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@ -7755,13 +7740,10 @@ public:
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addPatternIfTargetOpIsIllegal<DecomposeAtenZeroOp>(patterns);
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addPatternIfTargetOpIsIllegal<DecomposeAtenEyeOp>(patterns);
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addPatternIfTargetOpIsIllegal<DecomposeAtenEyeMOp>(patterns);
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// is-xxx ops
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addPatternIfTargetOpIsIllegal<DecomposeAtenIsnanOp>(patterns);
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addPatternIfTargetOpIsIllegal<DecomposeAtenIsinfOp>(patterns);
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addPatternIfTargetOpIsIllegal<DecomposeAtenIsneginfOp>(patterns);
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addPatternIfTargetOpIsIllegal<DecomposeAtenIsposinfOp>(patterns);
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addPatternIfTargetOpIsIllegal<DecomposeAtenNonzeroOp>(patterns);
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addPatternIfTargetOpIsIllegal<DecomposeAtenRandLikeOp>(patterns);
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addPatternIfTargetOpIsIllegal<DecomposeAtenHardsigmoidOp>(patterns);
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addPatternIfTargetOpIsIllegal<DecomposeAtenRelu6Op>(patterns);
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@ -78,10 +78,3 @@ func.func @torch.aten.type_as$fold(%arg0: !torch.tensor<[?], f16>, %arg1: !torch
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%0 = torch.aten.type_as %arg0, %arg1 : !torch.tensor<[?], f16>, !torch.tensor<[?,?],f16> -> !torch.tensor<[?], f16>
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return %0 : !torch.tensor<[?], f16>
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}
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// -----
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// CHECK-LABEL: func.func @torch.aten.nonzero
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func.func @torch.aten.nonzero(%arg0: !torch.vtensor<[3,4,5],f32>) -> !torch.vtensor<[3,4,5],si64> {
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%0 = torch.aten.nonzero %arg0 : !torch.vtensor<[3,4,5],f32> -> !torch.vtensor<[3,4,5],si64>
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return %0 : !torch.vtensor<[3,4,5],si64>
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}
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