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torch-mlir/test/npcomp-run-mlir
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Sean Silva 7b7f35744b [RefE2E] Add interesting control flow example. 
This also required adding a lowering for ForOp in our tensor->memref
conversion.
 		2020-09-21 12:25:24 -07:00
..
basic.mlir [RefE2E] Add assemblyFormat for TCF and TCP ops and tidy up. 2020-09-18 15:03:53 -07:00
broadcast.mlir [RefE2E] Add assemblyFormat for TCF and TCP ops and tidy up. 2020-09-18 15:03:53 -07:00
constant-add-scalar.mlir [RefE2E] Add assemblyFormat for TCF and TCP ops and tidy up. 2020-09-18 15:03:53 -07:00
constant-add.mlir [RefE2E] Add assemblyFormat for TCF and TCP ops and tidy up. 2020-09-18 15:03:53 -07:00
constant.mlir Make input file to npcomp-run-mlir be positional. 2020-07-13 16:02:19 -07:00
control-flow-basic.mlir [RefE2E] Add interesting control flow example. 2020-09-21 12:25:24 -07:00
identity.mlir Make input file to npcomp-run-mlir be positional. 2020-07-13 16:02:19 -07:00
invalid-broadcast.mlir [RefE2E] Add assemblyFormat for TCF and TCP ops and tidy up. 2020-09-18 15:03:53 -07:00
invalid-matmul.mlir [RefE2E] Add support for matmul. 2020-09-18 11:31:01 -07:00
invalid-num-inputs.mlir [RefE2E] Add assemblyFormat for TCF and TCP ops and tidy up. 2020-09-18 15:03:53 -07:00
matmul.mlir [RefE2E] Add support for matmul. 2020-09-18 11:31:01 -07:00
mixed-rank.mlir [RefE2E] Add assemblyFormat for TCF and TCP ops and tidy up. 2020-09-18 15:03:53 -07:00
multi-output.mlir [RefE2E] Add assemblyFormat for TCF and TCP ops and tidy up. 2020-09-18 15:03:53 -07:00
multiple-ops.mlir [RefE2E] Add assemblyFormat for TCF and TCP ops and tidy up. 2020-09-18 15:03:53 -07:00
scalar.mlir [RefE2E] Add assemblyFormat for TCF and TCP ops and tidy up. 2020-09-18 15:03:53 -07:00